1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) panel and a liquid crystal display thereof, and more particularly to an active matrix LCD suitable for displaying a dynamic image.
2. Description of the Related Art
The manufacturing technique for LCDs has progressed in the manufacture of high contrast displays with a wide view angle. However, for the dynamic image which displays a continuous movement, the image quality deteriorates due to a residual image phenomenon. Recently, there have been many relative driving methods to improve the image quality of LCDs, and the black data insertion method provided by NEC Corporation is one suitable solution upon the dynamic image issue. The prior art applies the voltage of a black datum in a sequence to the Liquid crystal (LC) capacitor of each pixel during a frame period so as to have an “impulse-type” effect on the same display as a cathode ray tube (CRT) does. Therefore, a user can never see an image displayed at a certain time overlapped with a previous image.
FIG. 1 shows the configuration of an LCD 10 and the gate pulses of a signal line and scanning lines in accordance with the U.S. Publication No. 2003/0001983. The scanning signals VG1–VGn sequentially input to their corresponding scanning lines G1–Gn 12, and a data signal VD for displaying an image inputs to a signal line D1 13. The scanning signals VG1–VGn all comprise two main gate pulses 111 and 112 during a vertical scanning period. The gate pulse 111 is applied to the scanning signal VG1 for selecting a thin film transistor (TFT) 141 so as to write a display datum 181 to the pixel electrode 151. Meanwhile, that the voltage of the pixel electrode 151 referring to the potential Vcom of a common electrode 16 is positive is defined as a positive polarity in the pixel. The scanning signals VG1–VGn, data signal VD, and potential Vcom are output from a driving circuit, which comprises a plurality of driving devices and logic devices. After the gate pulse 111 applied to the scanning line VG1 falls, the gate pulse 112 is next applied to the scanning signal VGj to turn on the TFT 142 and a black datum 182 is enabled to write a pixel electrode 152. At the same time, the display of the pixel corresponding to the pixel electrode 152 turns black from a gradation in a previous frame.
When the gate pulse 111 of the scanning signal VG1 enables the scanning line G1 of the first pixel line, the gate pulse 111 of the scanning signal VG2 will follow to enable the scanning line G2 of the second pixel line. The display datum 183 will be allowed to write a pixel electrode 152. Simultaneously, that the voltage of the pixel electrode 151 referring to the potential Vcom of a common electrode 16 is negative is defined as a negative polarity in the pixel. A black datum 184 following the display datum 183 will write the scanning line Gj+1 of the corresponding pixel line after the gate pulse 112 of the scanning signal VGj+1 outputs. In general cases, the outputs of the black data insertion and the display data are simultaneously executed far from one half of the frame period on the LCD 10. Due to the lack of sufficient charging time for writing a black datum to a LC capacitor, a plurality of the gate pulses 112 have to be separately applied to the scanning lines 12 so as to make the corresponding pixels turn true black.
FIG. 2 is a gate pulse diagram showing the datum signals and scanning signals in accordance with FIG. 1. In fact, the RC delay arises in the transmission of the scanning signal, which is especially relevant to the LCD with a large size or high resolution. A square gate pulse 111 gradually becomes a distorted gate pulse 111′ on the scanning line 12 at the end of the transmission. In other words, the existence of the gate delay will shorten the actually working time of a display datum, and TFT is delayed to completely turn itself off. For example, a WUGAN LCD (1,920×1,200 pixels) is suitable for a high definition television (HDTV), and the time H between the gate pulses 111 separately output from one scanning line and the next is no more than 13.3 μsecs. It is necessary to satisfy the equation of H=t1+t2+t3+t4, wherein t2 of the distorted gate pulse 111′ and t4 of the distorted gate pulse 112′ represent the gate delay times and thereof shorten the actually working times t1 of a display datum 181 and t3 of a black datum 182.
t1t2t3t4Case 15 μsecs2.5 μsecs3.3 μsecs2.5 μsecsCase 24 μsecs  3 μsecs3.3 μsecs  3 μsecs
In Case 1 of the above table, t2 and t4 are equal to 2.5 μsecs, and t1 and t3 are separately equal to 5 μsecs and 3.3 μsecs, respectively. In Case 2, t2 and t4 are equal to 3 μsecs, and t1 and t3 are separately equal to 4 μsecs and 3.3 μsecs, respectively. The definition of t1, t2, t3 and t4 are shown in FIG. 2. In conclusion, the prior art limits the charging time of the LC capacitor to the critically write-in time of a display datum 181, so the image quality deteriorates due to this limitation. Such an insufficient charging time is the bottleneck of upgrading the size and resolution of an LCD.